The present disclosure relates generally to a semiconductor device such as, an integrated circuit or portion thereof and, more particularly, to a method of forming a gate structure of a semiconductor device.
As technology progresses, transistor gate height is decreasing. For example, a typical gate height for a 90 nm process may be approximately 150 nm. This is compared to an approximately 60 nm gate height for a typical 32 nm process. A gate height is generally defined during the deposition of a polysilicon layer (for example, in either polysilicon gate or metal gate technologies). However, when a reduced gate height is desired, there are several issues. Implant processes (such as implanting a low-dose drain (LDD) or pocket (halo) region) into the substrate adjacent the gate structure may be difficult if the gate height is too low. In contrast, if the gate height too high shadow effects may occur. For example, the impurities implanted may penetrate beneath the gate structure. Furthermore, a polysilicon etching time for decreasing the gate height may be very short, for example, less than 5 seconds. Such etching processes may be difficult to accurately control.
Therefore, what is needed is an improved method of forming a gate structure.